User's Guide and General Information

Clock and Control Board

CCB'2004 for the EMU Peripheral and Track Finder Electronics, Production Version (October 2004)

Board status and location

 

CCB'2004 Clock and Control Board for the EMU Peripheral and Track Finder Electronics

  • PCB fabrication files Version 02/28/2005
  • PCB assembly files Version 02/28/2005

  • MPC'2004 Specification. Version 02/12/2007 (Board_ID[5..0] and Link_ID[1..0] added, CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB, sorting scheme was changed to allow zero-quality LCT's with vpf=1 to participate in sorting)
    • Configuration mcs file for the XC18V04 EPROM. Version 10/27/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 participate in sorting)
    • Configuration svf file for the XC18V04 EPROM. Version 10/27/2006 includes the  Board_ID[5..0] + Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 participate in sorting.

  • MPC'2004 Specification. Version 10/26/2006 (Board_ID[5..0] and Link_ID[1..0] added, CSR7 and CSR8 added to mask/unmask individually any LCT from any TMB)
  • Configuration mcs file for the XC18V04 EPROM. Version 10/26/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 do not participate in sorting)
  • Configuration svf file for the XC18V04 EPROM. Version 10/26/2006 (including Board_ID[5..0] and Link_ID[1..0], CSR7 and CSR8, zero-quality LCT's with vpf=1 do not participate in sorting).

  • MPC'2004 Specification. Version 04/26/2006 (Board_ID[5..0] and Link_ID[1..0] added)
    • Configuration mcs file for the XC18V04 EPROM. Version 04/26/2006 (including Board_ID[5..0] and Link_ID[1..0])
    • Configuration svf file for the XC18V04 EPROM. Version 04/26/2006 (including Board_ID[5..0] and Link_ID[1..0]).

  • MPC'2004 Specification. Version 11/24/2005 (Including transparent BC0)
    • Configuration mcs file for the XC18V04 EPROM. Version 11/24/2005 (Including transparent BC0)
    • Configuration svf file for the XC18V04 EPROM. Version 11/24/2005 (Including transparent BC0)

    • Configuration svf file to program XC18V04 EPROM. Version 10/20/2005
    • Configuration svf file to verify XC18V04 EPROM. Version 10/20/2005

    • Configuration mcs file for the XC18V04 EPROM. Version 04/23/2005
    • Configuration svf file to program XC18V04 EPROM. Version 04/23/2005
    • Configuration svf file to verify XC18V04 EPROM. Version 04/23/2005
    • Configuration svf file to erase XC18V04 EPROM. Version 04/23/2005

  • MPC2004 .ucf file

  • Eye diagram and jitter measurements at the SP input (differential outputs DOUTTXP/DOUTTXN of the TLK2501 receiver; 100 m multimode fiber; 1.6Gbps rate)

  • MPC2004 Schematic (pdf files)

  • MPC2004 special project with the LFSR-based 15-bit PRBS generators for the optical links. Identical PRBS generators for all three links. PRBS generators run continuously after power cycling. Links need to be initialized by sending the L1Reset command. The generators are reset by the BC0 pulse which is transmitted as a 16th bit in the datastream from the MPC to SP. Interface to TMBs, sorter unit, FIFO_A and FIFO_B are not available.
    • mcs file for XC18V04 EPROM
    • svf file for the XC18V04 EPROM
    • Simplified block diagram of the transmitter and receiver PRBS logic. BC0 in the transmitter part here is a 12.5 ns pulse derived from the 25 ns BC0 TTC command.

  • Firmware for the MPC2004, version 05/20/2008. Same as 10/27/2006, plus 16-bit L1Reset counter added. Available for read (base address + B4). Reset on "FPGA Soft Reset command.
  • Configuration mcs file for the XC18V04 EPROM. Version 05/20/2008
  • Configuration svf file for the XC18V04 EPROM. Version 05/20/2008.

  • MPC-to-SP Synchronization Procedure (L.Uvarov)

  • MPC2004 Xilinx project (zip) . Version 10/27/2006 (open with Xilinx ISE 6.2.03).
  • MPC2004 Xilinx project (zip) . Version 10/08/2008 (open with Xilinx ISE 6.2.03).

  • Example of IDCODE/USERCODE read procedure via JTAG from XC18V04 EPROM (.txt file)

  • Simplified TMB2005-to-MPC2004 data transmission test code (.txt file)

    • MPC'2002 for the EMU Peripheral Electronics (Initial Prototype, April 2002)

    Muon Port Card Mezzanine Card Mezzanine Card

    MPC'2000 for the EMU Peripheral Electronics

    This is the first prototype of MPC designed in 2000. The board is able to receive up to six trigger primitives from three Trigger Motherboards TMB'99, select three best and transmit them to Sector Receiver prototype designed at UCLA in 2000. The boards were used at the University of Florida for joint tests with a prototypes of Sector Receiver and Sector Processor modules.

    Muon Port Card 2000 Prototype

    Muon Sorter

    Muon Sorter receives up to 36 reconstructed muon primitives from 12 Sector Processors, selects the four best and transmits them to the Global Muon Trigger crate for further processing. Muon Sorter resides in the middle of the Track Finder crate and communicates with the Clock and Control Board (CCB) and Sector Processors over custom backplane.

    MS2005 (Production Version, July 2005)

    Board Status (Location, Firmware, Hardware, Mezzanines)

     

    MS2005 Board

  • MS2005 Schematic (pdf files)

  • Specification of the MS-to-GMT non-halogen copper cable

  • MS2005 Xilinx FPGA project (zip) . Version 09/07/2009 (open with Xilinx ISE 6.2.03).

  • MS2005 Xilinx FPGA project (zip) . Version 03/31/2009 (open with Xilinx ISE 6.2.03).

  • MS2005 Xilinx FPGA project (zip) . Version 06/26/2007 (open with Xilinx ISE 6.2.03).

  • MS2005 Xilinx PLD project (zip) . Version 08/16/2005 (open with Xilinx ISE 6.2.03).

    • MS2003 (First Version, February 2003)

    Muon Sorter Board

  • MS Schematic (pdf files)
  • EPROM Configuration file (.evf) for SCANPSC100F controller, version 12/10/2003
  • Configuration file (.jed) for XCR3128XL PLD, version 11/05/2003
  • National SCANPSC100FSC JTAG Controller
  • Mechanical Drawing of the backplane connectors, 12/06/2002
  • CSC Track Finder Crate Specification. December 2002.
  • Specification if the Interface Between the Regional Muon Triggers and the Global Muon Trigger. CMS Internal Note IN 2004/022 Version 1.00. June 8, 2004

    • Mezzanine Board for the MTF7 Muon Track Finder

    Production Version, February 2016

     

    Mezzanine board, Top MTF7 Baseboard with the mezzanine EMTF uTCA crate